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dual 64-and 256-position i 2 c nonvolatile memory digital potentiometers ad5251/ad5252 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures ad52 51: d u al 64-position resolution ad52 52: d u al 256-position resolution 1 k?, 10 k?, 50 k?, 100 k? non v ola t ile me mor y 1 st or es wiper setting w/writ e pr ot ec tion p o w e r- on refreshed with eem em settings in 300 s t y p eemem rewrite time = 540 s t y p resistanc e t o le r a nc e st or ed in non v ola t ile me mor y 12 e x tr a byt e s i n eemem f o r us er- d e f ined inf o rma tion i 2 c c o mpa t ible serial int e r f ac e d i r e c t r ead/wri t e ac c e ss of rd a c 2 and eemem r e gist ers p r edefined line ar incr ement/decr ement c o mmands p r edefined 6 db st ep change c o mmands s y nchr on ous or a y synchr onous dual channel upda te w i per setting read back 4 mhz ban d wi dth1 k? v e r s ion single sup p ly 2 . 7 v t o 5.5 v d u al s u p p ly 2 .25 v to 2 .75 v 2 sla v e a ddress dec o ding bits allow o p er a t ion o f 4 devic e s 100-y e ar t y pic a l da ta ret e ntio n t a = 5 5 c o p er a t ing t e mper a t ur e C40 c t o +85 c applic a t io ns mechanic al pot e ntiomet e r r e p l ac ement g e ner a l purpose d a c r e plac e m ent lc d p a n e l v co m adjustmen t w h it e led brig h t ness adjustm e n t rf base sta t ion po w e r amp bia s c o n t r o l p r ogr a mmable gain and off s e t c o ntr o l p r ogr a mmable v o ltage - t o - c ur r e nt c o n v ersion p r ogr a mmable pow e r sup p ly s e nsor c a libr a t ions fun d ame n t a l bl ock di a g r a m rdac1 regis- ter rdac3 regis- ter rdac1 rdac3 data control command decode logic address decode logic control logic ad5251/ ad5252 i 2 c serial interface power- on reset v dd a1 w1 b1 a3 w3 b3 v ss dgnd scl sda ad0 ad1 wp rdac eemem rab tol 03823-0-001 eemem power-on refresh fi g u r e 1 . 1 the terms nonvol atil e memory and eem em are use d inte rchange a bl y. 2 the te rms d i gital p o te ntio m e t e r and r d a c are us ed inte rchange a bl y. gener a l description the ad5251 /ad5252 a r e d u al-c ha nne l , i 2 c, n o n v o l a t il e m e m - o r y , dig i tal l y con t r o l l ed p o t e n t io m e t e rs wi t h 64 /256 p o si tio n s, r e s p ecti v e l y . th e s e devi ce s pe rf o r m th e sa m e e l ectr o n i c a d j u s t - m e n t f u n c t i o n s as m e chanic a l p o t e n t iomet e rs, t r immers, an d va r i ab le r e sis t o r s. th e p a r t s v e rs a t ile p r og ra mma b i l i ty al lo ws m u lt ipl e mo d e s of op e r a t i o n , i n clu d i n g re a d / w r i te a c c e ss i n t h e r d a c a n d eemem r e gi s t e r s , i n cr em en t/ d e cr e m en t o f re s i st anc e , re s i st anc e ch ange s i n 6 d b s c a l e s , w i p e r s e t t i n g r e ad b a ck, and e x t r a eemem fo r st o r in g us er -d ef in e d info r - m a t i on su ch a s me mor y d a t a f o r ot he r c o m p on e n t s , l o o k - u p ta b l e , o r sys t e m i d e n ti f i ca ti o n i n f o rm a t i o n . the ad5251 /ad5252 al lo w t h e h o s t i 2 c co n t rol l ers t o wr i t e a n y o f the 64- or 256-s t ep wi p e r s e t t in gs in t h e rd a c r e g i st ers a nd s t o r e t h e m in t h e eemem. on ce t h e s e t t ings a r e s t o r e d , th ey a r e r e s t o r ed a u t o m a ticall y t o th e r d a c r e gi s t e r s a t sys t em p o w e r - on; t h e s e t t in gs can als o be r e s t o r e d d y na mical l y . the ad5251 /ad5252 p r o v ide ad di tio n al in cr em en t, de cr em e n t , +6 db step cha n ge, a nd C6 d b step cha n ge i n sy n c hr on o u s o r asy n chr o n o us cha nnel up da te m o des. t h e i n cr em en t a n d d e cr e m en t fun c ti o n s all o w s t ep w i s e l i n e a r ad j u s t m e n t s, w h ile 6 db st ep c h a n g e s a r e e q u i vale n t t o do ub l i n g o r halvi n g t h e r d a c wi p e r s e t t in g . th es e f u n c t i o n s are u s e f u l for st e e p - sl op e non l i n e a r a d j u st me n t s su ch as w h ite led b r ig h t n e ss a nd a u dio vol u m e con t r o l. t h e p a r t s ha ve a p a te n t e d re s i st a n c e tol e r a nc e st or i n g f u nc t i on w h i c h e n abl e t h e us er t o acces s t h e eemem and ob t a i n t h e abs o l u t e e nd-t o - e nd r e sist a n ce va l u e s o f t h e r d a c s fo r p r e c i s io n a pplica t ion s . the ad5251 /ad5252 a r e a v ail a b l e in tsso p - 14 p a c k a g es in 1 k?, 10 k?, 50 k?, a nd 100 k? o p tio n s an d a l l p a r t s ca n o p era t e o v er t h e C40c t o +85 c ext e n d e d ind u s t r i al t e m p era t ur e ra ng e .
ad5251/ad5252 rev.0 | page 2 of 28 table of contents electrical characteristics ................................................................. 3 interface timing characteristics ................................................ 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function description .............................. 9 i 2 c interface timing diagram .................................................... 9 i 2 c interface general description ................................................ 10 i 2 c interface detail description ................................................... 11 rdac/eemem write ............................................................... 11 i 2 c compatible 2-wire serial bus ................................................ 15 typical performance characteristics ........................................... 16 operational overview .................................................................... 20 linear increment and decrement commands ...................... 20 6 db adjustments (doubling/halving wiper setting) ..... 20 digital input/output configuration ........................................ 21 multiple devices on one bus ................................................... 21 terminal voltage operation range ......................................... 21 power-up and power-down sequences .................................. 21 layout and power supply biasing ............................................ 22 digital potentiometer operation ............................................. 22 programmable rheostat operation ......................................... 22 programmable potentiometer operation ............................... 23 applications ..................................................................................... 24 lcd panel v com adjustment ..................................................... 24 current-sensing amplifier ....................................................... 24 adjustable high power led driver ........................................ 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 6/04revision 0: initial version
ad5251/ad5252 rev. 0 | page 3 of 28 electrical characteristics 1 k? version. v dd = 3 v 10% or 5 v 10%; v ss = 0 v or v dd /v ss = 2.5 v 10%; v a = +v dd , v b = 0 v, C40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resolution n ad5251/ad5252 6/8 bits resistor differential nonlinearity 2 r-dnl r wb , r wa = nc, v dd = 5.5 v, ad5251 C0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5252 C1 0.25 +1 lsb r wb , r wa = nc, v dd = 2.7 v, ad5251 C0.75 0.3 +0.75 lsb r wb , r wa = nc, v dd = 2.7 v, ad5252 C1.5 0.3 +1.5 lsb resistor nonlinearity 2 r-inl r wb , r wa = nc, v dd = 5.5 v, ad5251 C0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5252 C2 0.5 +2 lsb r wb , r wa = nc, v dd = 2.7 v, ad5251 C1 +2.5 +4 lsb r wb , r wa = nc, v dd = 2.7 v, ad5252 C2 +9 +14 lsb nominal resistor tolerance ?r ab /r ab t a = 25c C30 +30 % resistance temperature coefficent (?r ab /r ab ) 10 6 /?t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel resistance matching ?r ab1 /?r ab3 0.15 % dc characteristic potentiometer divider mode differential nonlinearity 3 dnl ad5251 C0.5 0.1 +0.5 lsb ad5252 C1 0.25 +1 lsb integral nonlinearity 3 inl ad5251 C0.5 0.2 +0.5 lsb ad5252 C2 0.5 +2 lsb voltage divider temperature coefficent (?v w /v w ) 10 6 /?t code = half scale 25 ppm/c full-scale error v wfse code = full scale, v dd = 5.5 v, ad5251 C5 C3 0 lsb code = full scale, v dd = 5.5 v, ad5252 C16 C11 0 lsb code = full scale, v dd = 2.7 v, ad5251 ?6 C4 0 lsb code = full scale, v dd = 2.7 v, ad5252 C23 C16 0 lsb zero-scale error v wzse code = zero scale, v dd = 5.5 v, ad5251 0 3 5 lsb code = zero scale, v dd = 5.5 v, ad5252 0 11 16 lsb code = zero scale, v dd = 2.7 v, ad5251 0 4 6 lsb code = zero scale, v dd = 2.7 v, ad5252 0 15 20 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 ax, bx c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 wx c w f = 1 khz, measured to gnd, code = half scale 95 pf common-mode leakage current i cm v a = v b = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = 2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5v, v ss = 0 v 0.8 v output logic high (sda) v oh r pull-up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull-up = 2.2 k? to v dd =5 v, v ss = 0 v 0.4 v
ad5251/ad5252 rev. 0 | page 4 of 2 8 p a r a me t e r sy m b o l c o nditions mi n ty p 1 ma x unit l e ak age c u r r ent i wp wp = v dd 5 a a0 l e ak age c u r r en t i a0 a0 = gnd 3 a i n put l e ak age c u rr en t ( o ther than wp and a0) i i v in = 0 v or v dd 1 a i n put c a pacitanc e 5 c i 5 p f power supplie s single -supply p o w e r r a nge v dd v ss = 0 v 2.7 5.5 v dual-supply p o w e r r a nge v dd /v ss 2 . 2 5 2 . 7 5 v p o sitiv e supply c u rr en t i dd v ih = v dd or v il = gnd 5 15 a nega tiv e supply c u rr en t i ss v ih = v dd or v il = gnd , v dd = +2.5 v , v ss = C2.5 v C 5 C 1 5 a eemem da ta st oring m o de cu r r e n t i dd_st ore v ih = v dd or v il = gnd 35 ma eemem da ta r e st oring m o de cu r r e n t 6 i dd_rest ore v ih = v dd or v il = gnd 2.5 ma p o w e r di ssip a ti on 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw p o w e r supply s e nsitivit y pss ?v dd = 5 v 10 % ?0.025 0.01 0.025 %/% ?v dd = 3 v 10 % C0.04 0.02 0.04 %/% d y na mic ch ara c teris t ics 5 , 8 bandw idth C3 db bw r ab = 1 k? 4 mh z t o tal har m onic distor tion t h d v a = 1 v r m s , v b = 0 v , f = 1 kh z 0.05 % v w s e ttling t ime t s v a = v dd , v b = 0 v 0.2 s r e sistor noise v o ltage e n_wb r wb = 500 ?, f = 1 kh z (ther m al noise only) 3 nv/ hz digital cr os stal k c t v a = v dd , v b = 0 v , measur e v w with ad jac e n t rd a c mak i ng full-sca l e change C 8 0 d b analog c o upling c at sig n al input a t a1 and measur e the output a t w3, f = 1 kh z C 7 2 d b 1 typical repr esents the av erage read ing at 25c and v dd = 5 v . 2 r e si st o r po si t i on n o n l i n ea ri t y error (r - i n l ) i s t h e d e vi a t i o n from an i d eal val u e meas ure d be tw een the maximum res i s t ance and the minimum res i s t anc e wiper posi t i on s. r - d n l m e a s ure s t h e rela t i ve st ep ch a n ge from i d ea l bet w een succ essi ve t a p posi t i on s . pa rt s a r e gua ra n t eed m o n o t o n i c, exc e pt r-dnl of ad5252 1 k? vers ion at v dd = 2.7 v, i w = v dd /r for b o th v dd = 3 v or v dd = 5 v. 3 inl and dnl are m e as ured at v w with the rda c c o nf igured a s a p o tentiometer d i vid e r s imil ar to a vol t age ou tput d/a converter. v a = v dd a n d v b = 0 v . d n l s p ecif ication l imits of 1 l s b maximum are guaranteed monotonic operating cond itions . 4 res i s t or terminal s a , b, and w have n o l imit ations on polarity with res p ect to each other. 5 gua r a n t eed by des i gn a n d n o t subj ect t o pro d uct i on t e st . 6 cmd 0 nop s h ould be activated af ter c m d 1 to minimiz e i dd_ r ead curre nt co ns umptio n. 7 p diss i s ca lcula t e d fr om i dd v dd = 5 v. 8 al l d y namic characteris t ics use v dd = 5 v.
ad5251/ad5252 rev. 0 | page 5 of 2 8 10 k?, 50 k?, 100 k? versio ns. v dd = +3 v 10% or + 5 v 10%. v ss = 0 v or v dd /v ss = 2.5 v 1 0 %. v a = +v dd , v b = 0 v, C40c < t a < + 85c, u n less otherwise noted. table 2. p a r a me t e r sy m b o l c o nditions mi n ty p 1 ma x unit dc chara c te ri s t i c s rheost a t mod e r e s o l u t i o n n ad5251/ad525 2 6 / 8 b i t s r e sistor diff er ential nl 2 r - d n l r wb , r wa = nc, a d 5251 ?0.75 0.1 +0.75 lsb r wb , r wa = nc, a d 5252 ?1 0.25 +1 lsb r e sistor nonline a r i t y 2 r - i n l r wb , r wa = nc, a d 5251 ?0.75 0.25 +0.75 lsb r wb , r wa = nc, a d 5252 ?2.5 1 +2.5 lsb nominal r e sisto r t o leran c e ?r ab /r ab t a = 25c ?20 +20 % r e sistanc e t e m p era tur e c o effic e n t (?r ab /r ab ) 10 6 / ? t 6 5 0 p p m / c w i per r e sistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channe l r e sista n c e m a tching ?r ab1 /?r ab2 r ab = 10 k?, 50 k? 0.15 % r ab = 100 k? 0.05 % dc chara c te ri stics po tentiome te r divid e r mode diff er en tia l non l inear i t y 3 d n l a d 5 2 5 1 ? 0 . 5 0 . 1 + 0 . 5 l s b a d 5 2 5 2 ? 1 0 . 3 + 1 l s b in t e g r a l n o n l i n e a r i t y 3 i n l a d 5 2 5 1 ? 0 . 5 0 . 1 5 + 0 . 5 l s b a d 5 2 5 2 ? 1 . 5 0 . 5 + 1 . 5 l s b v o ltage divider t e mpera tur e c o effic e n t (?v w /v w ) 10 6 /?t c o d e = half s c al e 15 p p m/c f u ll-s c ale er r o r v wfs e c o de = full scale , ad5251 ?1 ?0.3 0 lsb c o de = full scale , ad5252 ?3 ?1 0 lsb ze ro - s c a l e e r ro r v wzs e c o de = z e r o scale , ad5251 0 0.3 1 lsb c o de = z e r o scale , ad5252 0 1.2 3 lsb resist or te rmi n a l s vo l t a g e r a n g e 4 v a , v b , v w v ss v dd v capac i t a n c e 5 ax, bx c a , c b f = 1 kh z, measur ed t o gnd , c o d e = half s c al e 8 5 p f capac i t a n c e 5 wx c w f = 1 kh z, measur ed t o gnd , c o d e = half s c al e 9 5 p f c o mmon - m o de l e ak age cu r r e n t i cm v a = v b = v dd / 2 0 . 0 1 1 a digit a l in puts and outputs i n pu t l o gic h i gh v ih v dd =5 v , v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v i n p u t lo g i c low v il v dd = 5 v , v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss =2.5 v 0.6 v o utput l o g i c h i gh (sd a ) v oh r pul l -up = 2.2 k? to v dd = 5 v , v ss = 0 v 4.9 v o utput l o g i c l o w (sd a ) v ol r pul l -up = 2.2 k? to v dd = 5 v , v ss = 0 v 0.4 v l e ak age c u r r ent i wp wp = v dd 5 a a0 l e ak age c u r r en t i a0 a0 = gnd 3 a i n put l e ak age c u rr en t ( o ther than wp and a0) i i v in = 0 v or v dd 1 a i n put c a pacitanc e 5 c i 5 p f power supplie s single -supply p o w e r r a nge v dd v ss = 0 v 2.7 5.5 v
ad5251/ad5252 rev. 0 | page 6 of 28 parameter symbol conditions min typ 1 max unit dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = -2.5 v ?5 ?15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd, t a = 0c to 85c 35 ma eemem data restoring mode current 6 i dd_restore v ih = v dd or v il = gnd, t a = 0c to 85c 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss ?v dd = 5 v 10% ?0.005 +0.002 +0.005 %/% ?v dd = 3 v 10% ?0.01 +0.002 +0.01 %/% dynamic characteristics 5 , 8 C3 db bandwidth bw r ab = 10 k?/50 k?/100 k? 400/80/40 khz total harmonic distortion thd w v a = 1 vrms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v, r ab = 10 k?/50 k?/100 k? 1.5/7/14 s resistor noise voltage e n_wb 10 k?/50 k?/100 k?, code = midscale, f = 1 khz (thermal noise only) 9/20/29 nv/ hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full scale change -80 db analog coupling c at signal input at a1 and measure output at w3, f = 1khz -72 db 1 typical represents the av erage reading at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic, except r-dnl of ad5252 1 k? version at v dd = 2.7 v, i w = v dd /r for both v dd = 3 v or v dd = 5 v. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 4 resistor terminals a, b, and w have no limit ations on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 cmd 0 nop should be activated after cmd 1 to minimize i dd_read current consumption. 7 p diss is calculated from i dd v dd = 5 v. 8 all dynamic characteristics use v dd = 5 v.
ad5251/ad5252 rev. 0 | page 7 of 28 interface timing characteristics guaranteed by design, not subject to production test. see figure 3 for location of measured va lues. all input control voltages are specified with tr = tf = 2.5 ns (10% to 90% of 3 v), and timed from a voltage level of 1.5 v. switching characteristics are mea sured using both v dd = 3 v and 5 v. table 3. interface timing and eemem re liability characteristics (all parts). parameter symbol conditions min typ max unit interface timing scl clock frequency f scl 400 khz tbuf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for start condition t 5 0.6 s t hd;dat data hold time t 6 0 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s eemem data storing time t eemem_store 26 ms eemem data restoring time at power-on 1 t eemem_restore1 v dd rise time dependent. measure without decoupling capacitors at v dd and v ss . 300 s eemem data restoring time upon restore command or reset operation 1 t eemem_restore2 v dd = 5 v 300 s eemem rewritable time (delay time after power on or reset before eemem can be written) t eemem_rewrite 540 s flash/ee memory reliability endurance 2 100 kcycles data retention 3 100 years 1 during power-up, all outputs preset to midscale before restoring to the final eemem contents. rdac0 has the shortest, whereas rdac3 has the longest eemem data restoring time. 2 retention lifetime equivalent at junction temperature t j = 55c per jedec std. 22, method a117. retention lifet ime based on an activation energy of 0.6 ev derates with junction temperature. 3 when the part is not in operation, the sda and scl pins should be pulled to high. when these pins are pulled to low, the i 2 c interface at these pi ns conducts current of about 0.8 ma at v dd = 5.5 v and 0.2 ma at v dd = 2.7 v.
ad5251/ad5252 rev.0 | page 8 of 28 absolute maximum ra tings t a = 2 5 c, unle s s ot herwi s e not e d . table 4. p a r a me t e r r a t i n g v dd to gnd ?0.3 v , +7 v v ss to gnd +0.3 v , ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss , v dd m a ximum c u r r en t iwb , iw a p u lsed 20 ma i wb c o n t inuous ( r wb 1 k?, a o p en) 1 5 ma i wa c o n t inuous ( r wa 1 k?, b o p en) 1 5 m a i ab c o n t inuous (r ab = 1 k?/10 k?/50 k?/100 k?) 1 5 ma/500 a/ 100 a/50 a dig i tal i n puts and o utput v o ltage to gnd 0 v , 7 v o p era t ing t e mp er a tur e r a nge ?40c to +85c m a ximum junc tion t e mpera tur e (t j m a x ) 150c stor age t e mpera tur e ?65c to +150c l e ad t e mper a tur e (s older i ng ,10 sec) 300c v a por p h ase (60 sec) 215c i n fr ar ed (15 sec) 220c tssop - 14 thermal r e sistance 2 ja 136c/w s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . 1 maximum terminal current is boun ded by the maximum applied v o ltage a c ross a n y t w o of t h e a, b, a n d w t e rm i n a ls a t a gi ven r e si st a n ce, t h e maximum current handling of the sw i t ches, and the maxi m um power di ssi pa t i on of t h e p a cka g e. v dd = 5 v . 2 pa cka g e pow e r di s s i p a t i o n = (tj m ax ? t a )/ ja . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y .
ad5251/ad5252 rev. 0 | page 9 of 2 8 pin conf igura t ion and function description 1 2 3 4 5 6 7 ad0 wp w1 sda a1 b1 v dd 14 13 12 11 10 9 8 b3 a3 ad1 v ss scl dgnd w3 03823-0-002 ad5251/ ad5252 top view (not to scale) f i g u re 2. a d 52 51 /a d52 5 2 i n t s so p - 1 4 ta ble 5. pi n f u nct i on d e s c ri pt i o ns p i n no . m n emonic description 1 v dd p o sitiv e p o w e r sup p ly p i n. c o nn ec t +2.7 v to +5 v f o r single sup p ly or 2.7 v f o r d u al sup p ly , wher e v dd C v ss 5.5 v . v dd must be able t o sour c e 35 ma f o r 26 ms when st oring da ta t o eemem. 2 a d 0 i 2 c d evic e a ddr ess 0. ad0 and ad1 allo w f o ur ad5251/ad525 2s to be addr essed . 3 wp wr i t e pro t e c t , ac t i ve low . v wp v dd + 0.3 v . 4 w1 w i per t e r minal of rd a c 1. v ss v w1 v dd . 1 5 b1 b t e r minal of rd a c 1. v ss v b1 v dd . 1 6 a1 a t e rminal of rd a c 1. v ss v a1 v dd . 1 7 s d a serial da ta i n put/ o utput p i n. sh if ts in one bit a t a time on positi v e cl ock edges . msb loaded first. o p en- d r a in mosfe t r e quir es pull-up r e sist or . 8 v ss nega tiv e sup p ly . c o nnec t to 0 v f o r single sup p l y or C2.7 v f o r dual sup p ly , wh ere v dd C v ss +5.5 v . i f v ss is used , other than g r ounded , in dual supply , v ss must be able t o sink 35 ma f o r 26 ms when st oring da ta t o ee mem. 9 s c l s e r i al i n put r e gister clock p i n. s h if ts in one bit at a time on posit iv e cl ock edges . v scl (v dd + 0.3 v ) . p u ll-up r e sistor i s rec o mmend ed f o r scl to ensur e minimum po w e r . 10 dgnd digital gr ound . c o nnec t to system anal og gr ou nd a t a single p o in t. 1 1 a d 1 i 2 c d evic e a ddr ess 1. ad0 and ad1 allo w f o ur ad5251/ad525 2s to be addr essed . 12 a3 a t e rminal of rd a c 3. v ss v a3 v dd . 1 13 b3 b t e r minal of rd a c 3. v ss v b3 v dd . 1 14 w3 w t e r minal of rd a c 3. v ss v w3 v dd . 1 1 for q u a d - c h a n n e l devi ce so ft wa re c o m p a t i b i l i t y, t h e dua l pot e n t i om et ers i n t h e pa rt s a r e de si g n a t ed a s r d a c1 a n d r d a c3. i 2 c in terf a c e timing d i a g r a m t 1 scl sd a ps p 03823-0-003 t 3 t 2 t 8 t 9 t 8 t 9 t 4 t 5 t 7 t 6 t 10 fi g u r e 3 . i 2 c ti mi ng d i ag r a m
ad5251/ad5252 rev. 0 | page 10 of 28 i 2 c interf ace general des cri ption r/w a/a s slave address (7-bit) a 0 write a instructions (8-bit) data transferred (n bytes + acknowledge) data (8-bit) p 03823-0-004 from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) r/w = read enable at high and write enable at low fi g u r e 4 . i 2 cm a s t er w r it ing d a t a t o slave r/w a s slave address (7-bit) 1 read data transferred (n bytes + acknowledge) data (8-bit) data (8-bit) p 03823-0-005 a a fi g u r e 5 . i 2 cm a s t er r e ading d a t a f r om sl ave r/w r/w s slave address (7-bit) read or write (n bytes + acknowledge) slave address data a s 03823-0-006 repeated start read or write direction of transfer may change at this point a a/a (n bytes + acknowledge) data p a/a fi g u r e 6 . i 2 c combined w r it e/read
ad5251/ad5252 rev. 0 | page 11 of 28 i 2 c interf ace det ail description 0 write 03823-0-007 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 a p data 0 (1 byte + acknowledge) slave address instructions and address cmd/ reg ee/ rdac 0 reg a/ a from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) r/w = read enable at high and write enable at low cmd/reg = command enable bit, logic high/register access bit, logic low ee/rdac = eemem register, logic high/rdac register, logic low a4, a3, a2, a1, a0 = rdac/eemem register addresses f i gur e 7 . si ngle w r it e mo de 0 write 03823-0-008 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 p a a rdac1 data rdac3 data 0 (n bytes + acknowledge) rdac slave address rdac instructions and address cmd/ reg ee/ rdac 0 reg a/ a f i gure 8. consecut i v e w r ite m o de tab l e 6. add r esses for writin g data by te con t en ts to rdac registers (r/ w = 0, cm d/ reg = 0, ee/ rdac = 0) a 4 a 3 a 2 a 1 a 0 rd a c da ta byte de scrition 0 0 0 0 0 r e ser v e d 0 0 0 0 1 rd a c 1 6- or 8 bit wiper setting (2 msbs of ad5251 ar e x) 0 0 0 1 0 r e ser v e d 0 0 0 1 1 rd a c 3 6- or 8 bit wiper setting (2 msbs of ad5251 ar e x) 0 0 1 0 0 r e ser v e d : : : : : 0 1 1 1 1 r e ser v e d rd a c /eeme m write s e t t in g t h e w i p e r p o si t i o n r e q u i r es a n rd a c w r i t e o p er a t io n. the sin g l e wr i t e o p er a t io n is sho w n i n f i gur e 7 , a nd t h e co n s e c u t i v e wr i t e o p era t io n is sh o w n i n f i gur e 8. i n t h e co n s e c u t i v e wr i t e o p era t io n, if t h e rd a c is s e le c t e d and t h e addr es s s t a r ts a t 00001, th e f i rst da ta b y t e g o es to rd a c 1 and t h e s e con d da t a b y t e g o es t o r d a c 3. th e r d a c addr ess is shown i n t a bl e 6 . w h i l e t h e r d a c w i p e r s e t t in g is co n t r o l l e d b y a sp e c if ic rd a c r e g i s t er , e a ch r d a c r e g i s t er co r r es p o n d s t o a sp e c if ic eemem lo ca t i on, w h ich p r o v ide s n o n v ol a t i l e wi p e r st o r age f u n c t i o n a l i t y . the ad dr ess e s ar e sh o w n i n t a ble 7. t h e sing le a nd co n s e c u t i v e wr i t e o p era t io ns a p pl y als o t o eemem wr i t e o p era t io n s . ther e a r e 12 n o n v ol a t i l e m e m o r y lo ca t i o n s: eemem4 t o eemem15. u s ers ca n st o r e a t o tal o f 12 b y t e s of inf o r m a t io n, su ch a s me mor y d a t a for ot he r c o m p o n e n t s , l o o k - u p t a bl e s , or sys t em i d en t i f i c a t i o n info r m a t i o n. i n a wr i t e op era t io n t o t h e eem em r e g i s t ers, t h e de vic e dis a b l e s th e i 2 c in t e r f ac e d u r i ng t h e i n ter n al wr i t e c y cle . a c k n o w le dg e p o l l in g is r e q u ire d t o de t e r m i n e t h e com p let i on o f t h e wr i t e c y cle . s e e eemem w r i t e- a c k n o w le dg e p o l l in g .
ad5251/ad5252 rev. 0 | page 12 of 28 ta ble 7. a d dre s s e s for wri t i n g ( s t o ri ng) rd a c set t i ngs a nd user-defi n e d data to eeme m registers (r / w = 0, cmd/ reg = 0, ee/ rdac = 1) a 4 a 3 a 2 a 1 a 0 da ta byte de scription 0 0 0 0 0 r e ser v e d 0 0 0 0 1 stor e rd a c 1 setting to eemem1 1 0 0 0 1 0 r e ser v e d 0 0 0 1 1 stor e rd a c 3 setting to eemem3 1 0 0 1 0 0 stor e user da ta to eemem4 0 0 1 0 1 stor e user da ta to eemem5 0 0 1 1 0 stor e user da ta to eemem6 0 0 1 1 1 stor e user da ta to eemem7 0 1 0 0 0 stor e user da ta to eemem8 0 1 0 0 1 stor e user da ta to eemem9 0 1 0 1 0 stor e user da ta to eemem10 0 1 0 1 1 stor e user da ta to eemem11 0 1 1 0 0 stor e user da ta to eemem12 0 1 1 0 1 stor e user da ta to eemem13 0 1 1 1 0 stor e user da ta to eemem14 0 1 1 1 1 stor e user da ta to eemem15 1 u s e r ca n s t or e a n y o f t h e 64 rd a c s e tti n g s for ad5251 or a n y o f th e 256 rd a c s e tti n g s f o r ad5252. rdac/eemem read te ad21 /ad22 r o ide tw o di er en t rd a c o r eemem re a d o e r a t i o ns o r e am l e i g u re sow s t e m e t o d o r e a d i n g t e r d a c 0 t o r d a c 3 c o n t e n t s w i t o u t s e c i yi n g t e addr es s as s u min g a d dr es s r d a c 0 was alr e ady s e le c t e d r o m t e r e i ou s o e r a t i o n r d a c ot e r t a n a d d r e s s 0 i s s e lec t e d r e io u s l y r e ad ack s t ar ts wi t a ddr ess o l l o w ed y 1 a nd s o on i gur e 10 ill u s t ra t e s a rando m rd a c o r eemem r e ad o era t ion tis o era t ion lets u s ers s e c i y w i c rd a c o r eemem r e g i s t er is r e ad y i r s t is s u ing a d u mm y wr i t e co mman d to c a n ge t e r d a c addr ess o in ter a nd t en r o c e e d i n g wi t t e r d a c r e a d o er a t io n a t t e ne w a ddr ess lo ca tion tab l e 8. add r esses for read i n g (restorin g ) rdac settin g s and user data from ee mem ( r / w = 1 , c m d/ reg = 0, ee/ rdac = 1) a 4 a 3 a 2 a 1 a 0 da ta byte de scription 0 0 0 0 0 r e ser v e d 0 0 0 0 1 r e ad rd a c 1 s e t t ing fr om eemem1 0 0 0 1 0 r e ser v e d 0 0 0 1 1 r e ad rd a c 3 s e t t ing fr om eemem3 0 0 1 0 0 r e ad user da ta f r om e e m e m 4 0 0 1 0 1 r e ad user da ta f r om e e m e m 5 0 0 1 1 0 r e ad user da ta f r om e e m e m 6 0 0 1 1 1 r e ad user da ta f r om e e m e m 7 0 1 0 0 0 r e ad user da ta f r om e e m e m 8 0 1 0 0 1 r e ad user da ta f r om e e m e m 9 0 1 0 1 0 r e ad user da ta f r om e e m e m 1 0 0 1 0 1 1 r e ad user da ta f r om e e m e m 1 1 0 1 1 0 0 r e ad user da ta f r om e e m e m 1 2 0 1 1 0 1 r e ad user da ta f r om e e m e m 1 3 0 1 1 1 0 r e ad user da ta f r om e e m e m 1 4 0 1 1 1 1 r e ad user da ta f r om e e m e m 1 5 1 read 03823-0-009 s 0 1 0 1 1 a d 1 a d 0 1 a p a rdac1 eemem or register data rdac3 eemem or register data rdac slave address (n bytes + acknowledge) a f i gure 9. r d a c cu r r ent r e ad (r estr ic ted to p r ev i o usly s e l e c t ed address sto r ed in the r e g i ster). p s slave address 0 write slave address instruction and address a 1 s 03823-0-010 repeated start 1 read a 0a (n bytes + acknowledge) rdac or eemem data a/a f i gur e 1 0 . rd a c or eemem r a ndom r e a d
ad5251/ad5252 rev. 0 | page 13 of 28 rdac/eemem quick commands the ad5251 /ad5252 f e a t ur e 1 2 q u ic k co mman ds tha t f a cili ta te e a s y m a n i pu l a t i on of r d a c w i p e r s e tt i n g s a n d pro v i d e r d a c - to - e e m e m stor i n g a n d re s t or i n g f u nc t i on s . t h e c o m m a nd fo r m a t is sh o w n in f i gur e 11 a nd t h e co mm a n d des c r i p t ion s a r e shown i n t a bl e 9 . 0 write 03823-0-011 1 cmd s 0 1 0 1 1 a d 1 a d 0 0 a c 3 c 2 c 1 c 0 a 2 a 1 a 0 a p rdac slave address cmd/ reg from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) ad1, ad0 = i 2 c device address bits. must match with the logic states at pins ad1, ad0 r/w = read enable bit, logic high/write enable bit, logic low cmd/reg = command enable bit, logic high/register access bit, logic low c3, c2, c1, c0 = command bits a2, a1, a0 = rdac/eemem register addresses f i g u re 11. r d a c q u ick com m a nd w r i t e ( d u m m y w r it e) table 9. rdac -to-eemem interface and rd ac op eration quick comma n d bits (cmd/ reg = 1, a2 = 0) c 3 c 2 c 1 c 0 c o mmand des c r i p t i o n 0 0 0 0 n o p 0 0 0 1 r e st or e eemem ( a 1, a0) t o rd a c ( a 1, a0) 1 0 0 1 0 stor e rd a c ( a 1, a0) to ee mem ( a 1, a0) 0 0 1 1 d e cr emen t rd a c ( a 1, a0) 6 db 0 1 0 0 d e cr emen t all rd a c s 6 db 0 1 0 1 d e cr emen t rd a c ( a 1, a0) one step 0 1 1 0 d e cr emen t all rd a c s one step 0 1 1 1 r e set: r e stor e eem em s to all rd a c s 1 0 0 0 i n cr emen t rd a c s ( a 1, a0) 6 db 1 0 0 1 i n cr emen t all rd a c s 6 db 1 0 1 0 i n cr emen t rd a c s ( a 1, a0) one step 1 0 1 1 i n cr emen t all rd a c s one step 1 1 0 0 r e ser v e d : : : : 1 1 1 1 r e ser v e d 1 this command l e a v es the d e vice in the ee me m rea d pow e r s t ate, which consumes p o wer. users s h ould iss u e the n o p command to ret u rn t h e devi ce t o t h e i d le st a t e. table 10. a ddr ess table for r e ading toleran c e (cmd/ reg = 0, ee/ rdac = 1, a4 = 1 ) a 4 a 3 a 2 a 1 a 0 da ta byte de scrition 0 0 0 0 0 r e ser v e d : : : : : 1 1 0 0 1 r e ser v e d 1 1 0 1 0 sig n and 7-bit integer v a lues of rd a c 1 toler a nce (r ead only) 1 1 0 1 1 8-bit decimal v a lue of rd a c 1 toler a nc e (r ead only) 1 1 1 0 0 r e ser v e d 1 1 1 0 1 r e ser v e d 1 1 1 1 0 sig n and 7-bit integer v a lues of rd a c 3 toler a nce (r ead only) 1 1 1 1 1 8-bit decimal v a lue of rd a c 3 toler a nc e (r ead only)
ad5251/ad5252 rev. 0 | page 14 of 28 03823-0-012 aa d7 d6 d5 d4 d3 d2 d1 d0 sign sign 7 bits for integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a d7 d6 d5 d4 d3 d2 d1 d0 8 bits for decimal number 2 ?8 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 f i gure 1 2 . f o rma t of st or ed t o l e r a nce in si gn m a gni t ude f o rm a t wi th bi t p o siti o n des c ri pt i o ns . (uni t i s p e r cent. o n ly da ta b y te s ar e sho wn.) r ab tolerance stored in read-only m e mo ry the ad5251 /ad5252 f e a t ur e p a t e n t e d r ab t o lera n c es st o r a g e i n t h e n o n v ol a t i l e m e m o r y . th e t o lera n c e o f e a ch cha nne l is st o r e d in t h e me m o r y d u r i n g t h e fac t or y p r o d uc t i o n a nd can b e r e ad b y us ers a t an y t i me . the k n o w l e dg e o f s t o r e d tolera n c e , w h ich is t h e a v er a g e o f r ab o v er al l co des (s ee f i gur e 2 8 ), al lo ws us ers to pre d i c t r ab a c c u ra te ly . this fe a t ur e is va lua b l e fo r p r e c isio n, rh e o st a t m o de, a nd o p e n -lo o p a p plic a t io n s w h er e k n o w le dge o f a b s o l u t e r e sist an ce is cr i t ic a l . the s t o r e d t o lera n c es r e side i n t h e r e ad-o nl y mem o r y , an d a r e exp r es s e d as a p e r c en t a ge . the tolera n c e is s t o r e d i n tw o m e m o r y lo ca tion s (s ee t a b l e 10 ). the da t a f o r m a t o f t h e t o lera n c e is in si g n ma g n i t ude b i na r y fo r m . an exa m ple is s h o w n in f i gur e 11. i n t h e f i rst m e m o r y lo ca tion, t h e ms b is desig n a t e d fo r t h e sig n (0 = + a nd 1= C) a nd t h e 7 ls bs a r e d e sign a t ed f o r th e in t e g e r p o r t io n o f th e t o lera n c e. i n t h e s e co nd m e m o r y lo ca t i on, a l l ei g h t da t a b i ts a r e desig n a t e d fo r t h e de cim a l p o r t io n o f toler a n c e. a s sh o w n in t a b l e 10 an d f i gur e 12 fo r exa m ple , if t h e ra te d r ab = 10 k? a nd t h e da ta r e ad back f r o m a ddr es s 11000 sh o w s 0001 1100 a nd a d dr es s 11001 s h o w s 00 00 1111, th en rd a c 0 t o leran c e ca n be calc u l a t e d as ms b: 0 = + n e xt 7 ms b: 00 1 1100 = 28 8 ls b: 0000 1111 = 15 2 C8 = 0.06 t o lera n c e = +2 8.06% an d t h er efo r e r ab_a ct u a l = 12. 806 k? eemem write-acknowledg e polling af t e r e a ch wr i t e o p era t io n t o t h e eemem r e g i s t ers, a n in ter n al wr i t e c y cle b e g i n s . th e i 2 c in t e r f ace o f t h e de vice is dis a b l e d . t o det e r m i n e if t h e in t e r n al wr i t e c y cle is co m p let e a nd t h e i 2 c in t e r f ace is enab le d , i n t e r f ace p o l l in g ca n b e exe c u t e d . i 2 c in ter f ace p o l l i n g ca n b e cond uc te d b y s e ndin g a st a r t con d i t ion fol l o w e d b y t h e s l a v e addr es s + t h e wr i t e b i t. i f t h e i 2 c in t e r f ace r e s p o n ds w i t h an a c k, t h e wr i t e c y cle is co m p let e an d t h e in t e r f ace is r e ady t o p r o c e e d w i t h f u r t h e r o p era t io n s . o t h e r - wis e , i 2 c in t e rf ac e po ll i n g c a n be r e pea t ed un til i t s u c c eed s . c o mman d s 2 and 7 a l s o r e q u ire ack n o w le dge p o l l in g. eemem write protection se t t i n g th e wp p i n t o a log i c l o w a f t e r eemem p r og ra mmin g p r o t e c ts t h e m e m o r y a n d rd a c r e g i s t ers f r o m f u t u r e wr i t e o p er a t io n s . i n t h is m o de, t h e e e mem a nd r d a c r e ad o p era t io n s op er a t e as n o r m al . w h en wr i t e p r ot e c t i o n is ena b le d, c o m m a nd 1 (resto r e f r o m eemem to rd a c ) and c o mmand 7 (r es et) f u nc t i o n no r m a l ly to a l lo w rd a c s e t t i n gs t o b e r e f r es h e d f r o m t h e eemem t o t h e rd a c r e g i s t ers.
ad5251/ad5252 rev.0 | page 15 of 2 8 i 2 c compa t ible 2-wire serial bus sd a frame 1 slave address byte frame 2 instruction byte scl ack. by ad525x ack. by ad525x ack. by ad525x frame 1 data byte stop by master 03823-0-013 start b y master 0 1 1 0 11 ad1 ad0 r/w x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 9 1 9 1 9 f i g u re 13. gen e r a l i 2 c w r it e p a tt ern 03823-0-014 sda frame 1 slave address byte frame 2 rdac register scl ack. by ad525x no ack. by master stop by master start by master 0 1 1 0 11 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 91 9 r/w f i g u re 14. gen e r a l i 2 c read p a tt ern the f i rs t b y t e o f th e ad5251/ad5252 is a sla v e addr es s b y t e (s e e f i gur e 12 and f i gur e 13). i t has a 7-b i t sl a v e addr ess a nd an r/ w b i t. th e 5 m s bs o f t h e s l a v e addr es s a r e 010 11, a nd t h e fol l o w in g 2 ls b s a r e det e r m i n e d b y t h e s t a t es of t h e ad1 and ad0 p i n s . ad1 a nd ad0 a l lo w t h e us er t o plac e u p t o fo ur p a r t s on one bu s . ad5251/ad52 52 ca n be con t r o l l ed via an i 2 c co m p a t i b le s e r i al b u s, a nd a r e conn e c te d to t h is b u s as sl a v e de v i ces. t h e 2 - w i r e i 2 c s e r i al b u s p r o t o c ol (s ee f i gu r e 13 a n d f i gure 14) f o l l o w s: 1. the mast er ini t i a t e s a da t a t r a n s f er b y es t a b l ishi n g a s t a r t co n d i ti o n , s u ch th a t s d a g o e s f r o m h i g h t o lo w wh ile scl is hig h (s ee f i g u r e 13). the f o l l o w in g b y t e is t h e s l a v e addr es s b y t e , w h ich co n s ists o f t h e 5 m s bs o f a s l a v e addr es s def i n e d as 01011. the next tw o b i ts a r e ad1 an d ad0, i 2 c de vice addr es s b i ts. d e p e n d in g on t h e s t a t es o f t h e i r ad1 and ad0 b i ts, fo ur p a r t s ca n b e a ddress e d on t h e s a m e b u s. th e las t l s b , t h e r/ w bit , d e t e r m i n e s w h et h e r da t a is r e ad f r o m o r wr i t t e n t o t h e sla v e de vic e . the sla v e w h os e addr ess co r r es p o n d s t o t h e t r an smi t t e d addr ess r e sp o nds b y p u l l ing t h e s d a l i n e lo w d u r i n g t h e nin t h clo c k p u ls e (t his is ca l l e d a n ack n o w le dge b i t). a t t h is s t a g e, al l o t h e r de vices on t h e b u s r e ma in idl e w h i l e t h e s e l e c t e d d e v i c e w a i t s for d a t a to b e w r it te n to or re a d f r om it s s e r i a l re g i s t e r . 2. i n t h e wr i t e m o de (excep t w h e n r e s t o r in g ee mem t o t h e rd a c r e g i st er), th er e is an in s t r u c t io n b y t e tha t f o l l o w s t h e s l a v e addr es s b y t e . th e ms b o f t h e i n s t r u c t i o n b y te is labe le d cm d/ reg . ms b = 1 ena b le s cmd , t h e comman d in st r u c t io n b y t e ; ms b = 0 ena b l e s gen e ra l r e g i ster wr i t i n g. the t h ir d ms b i n t h e i n st r u c t ion b y te, l a b e le d ee/ rd a c , is t r ue o n ly w h e n ms b = 0 o r is in ge n e ra l wr i t i n g mo de . ee ena b les t h e eemem r e g i s t er a n d reg ena b les th e rd a c r e g i st er . the 5 ls bs, a4 t o a0, desig n a t e t h e addr esses o f the eemem a n d rd a c r e g i s t er s, (see f i gur e 7 a nd f i gur e 8). w h en m s b = 1 o r wh en in cm d mo de , t h e fo u r bi ts fol l o w ing m s b ar e c3 to c1 , w h ich co r r es p o n d t o 12 p r edef in e d ee mem co n t r o ls a nd q u ick co mman d s; t h e r e a l s o a r e fo ur fac t o r y r e s e r v e d co mma nds. the 3 ls bsa 2, a1, an d a0 a r e fo ur addr ess e s, b u t o n ly 001 a nd 011 a r e us ed f o r rd a c 1 a nd rd a c 3, r e s p ec ti ve l y (s e e f i gur e 10). af t e r ack n o w le dg in g t h e inst r u c t io n b y t e , t h e last b y te i n t h e wr i t e m o de is t h e da t a b y t e . d a t a is tra n smi t t e d o v e r th e s e r i al b u s in s e q u e n ce s o f nin e c l o c k pu l s e s ( e i g ht d a t a b i t s f o l l ow e d by a n a c k n ow l e d g e b i t ) . t h e t r a n s i ti o n s o n th e s d a l i n e m u s t oc cu r d u ri n g th e l o w p e r i o d o f scl and r e ma i n st ab l e d u r i ng t h e h i g h p e r i o d o f scl (s ee f i gur e 13). 3. i n c u r r en t r e ad m o de , t h e rd a c 0 da t a b y te imm e dia t e l y fol l o w s t h e ack n o w le dg m e n t o f t h e s l a v e addr es s b y t e . a f t e r a n a c kn o w l e d g em en t , rd a c 1 f o ll o w s , t h en rd a c 2, a nd s o o n (t h e re is a s l ig h t dif f er en ce in wr i t e m o de , w h er e t h e last eig h t da t a b i ts r e p r es e n t i n g r d a c 3 da t a a r e fol l o w e d b y a no ack n o w le dge b i t). simi la rly , t h e tra n si ti o n s o n t h e s d a lin e m u s t occur d u r i n g th e lo w p e r i o d o f scl and r e ma i n st ab l e d u r i ng t h e h i g h p e r i o d o f s c l ( s e e fi g u re 1 4 ) . a n ot he r re a d i n g me t h o d , r a nd o m re a d me t h o d , i s sh ow n i n fi g u re 1 0 . 4. w h en all d a t a b i t s ha v e been r e a d o r w r i t t e n , a s t o p co ndi t i on is est a b l ish e d b y t h e mast er . a st o p c o n d i t ion is def i n e d as a lo w - to -hi g h t r a n s i t i o n o n t h e sd a l i ne w h i l e scl is hig h . i n wr i t e m o de , t h e mas t er p u l l s t h e s d a l i n e hig h d u r i n g t h e 10t h clo c k p u ls e t o est a b l i s h a sto p co ndi tion (s ee f i gur e 13). i n r e ad m o de , t h e mas t er is s u es a n o ack n o w le dge fo r t h e ni n t h cl o c k p u ls e, i . e., t h e sd a l i n e r e ma in s hig h . th e mas t er t h e n b r in gs t h e sd a line lo w be f o r e th e 10 th clo c k p u ls e, w h ich go es hig h t o e s t a b l i s h a sto p co nd i t io n ( s e e f i gur e 14).
ad5251/ad5252 rev.0 | page 16 of 2 8 typical perf orm ance cha r acte ristics r-inl (ls b ) code (decimal) 03823-0-015 t a = ? 40c, +25 c, +85c, +125c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 3 2 6 4 9 6 128 160 192 224 256 f i g u re 15. r-inl v s . code r-dnl (ls b ) code (decimal) 03823-0-016 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 3 2 6 4 9 6 128 160 192 224 256 t a = ? 40c, +25c, +85 c, +125c f i g u re 16. r-dnl v s . code inl ( l sb) code (decimal) 03823-0-017 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 3 2 6 4 9 6 128 160 192 224 256 t a = ? 40 c, +25c, +85c, +125c f i g u re 17. inl v s . code inl ( l sb) code (decimal) 03823-0-018 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 3 2 6 4 9 6 128 160 192 224 256 t a = ? 40 c, +25c, +85c, +125c f i g u re 18. dnl v s . code s u p p l y curre nt ( a) temperature ( c) 03823-0-019 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 120 i dd @ v dd = +5.5v i dd @ v dd = +2.7v i ss @ v dd = +2.7v, v ss = ? 2.7v f i gure 19. sup p l y current v s . t e mper at ur e digital input voltage (v) 03823-0-020 0.0001 0.01 0.001 0.1 1 10 01 234 56 v dd = 5.5v v dd = 2.7v i dd (ma) f i gure 20. sup p l y current v s . d i gita l i n put v o ltag e , t a = 2 5 c
ad5251/ad5252 rev. 0 | page 17 of 28 r wb ( ? ) v bias (v) 03823-0-021 20 0 40 60 80 100 120 140 160 200 240 180 220 1 0 2 34 56 v dd = 2.7v t a = 25 c v dd = 5.5v t a = 25 c data = 0x00 f i gur e 2 1 . wi p e r resi sta n c e vs . v bi as temperature ( c) 03823-0-022 ?6 ?4 ?2 0 2 4 6 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 120 ? r wb (%) f i gure 2 2 . change o f r ab v s . t e mper atur e code (decimal) 03823-0-023 0 50 60 70 20 10 30 40 80 90 0 3 2 6 4 9 6 128 160 192 224 256 rheostat mode tempco (ppm/ c) v dd = 5v t a = ? 40c/+85 c v a = v dd v b = 0v f i gur e 2 3 . ad52 52 r h e o sta t m o de t e m p c o ? r wb /? t v s . code code (decimal) 03823-0-024 0 20 25 10 5 15 30 0 3 2 6 4 9 6 128 160 192 224 256 potentiometer mode tempco (ppm/ c) v dd = 5v t a = ? 40c/+85 c v a = v dd v b = 0v f i gur e 2 4 . ad52 52 p o t e nt i o m e t e r mode t e m p c o ? v wb /?t vs . c o de ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-025 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 25. ad5252 g a in vs. f r equ e nc y vs. c o de , r ab = 1 k? ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-026 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 26. ad5252 g a in vs. f r equ e nc y vs. c o de , r ab = 10 k?
ad5251/ad5252 rev. 0 | page 18 of 28 ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-026 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 27. ad5252 g a in vs. f r equ e nc y vs. c o de , r ab = 50 k? ?6 0 ?4 8 ?2 4 ?1 2 0 ?3 6 ?5 4 ?3 0 ?1 8 ?6 ?4 2 gain ( d b) 1k 10k 10 100 100k 1m 10m frequency (hz) 03823-0-028 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 f i gure 28. ad5252 g a in vs. f r equ e nc y vs. c o de , r ab = 10 0 k? ? r ab ( ? ) code (decimal) 03823-0-029 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 20 40 60 80 100 0 3 2 6 4 9 6 128 160 192 224 256 100k ? 10k ? 50k ? v dd = 5.5v 1k ? f i gur e 2 9 . ad52 52 ? r ab vs. c o d e , t a = 25 c clock frequency (hz) 03823-0-030 0 0.6 0.4 0.2 0.8 1.0 1.2 1 100 10 1k 10k 100k 1m 10m v dd = 2.7v t a = 25 c v dd = 5.5v i dd (ma) f i gure 3 0 . sup p l y current vs . di gi tal input cl ock f r equenc y 03823-0-031 digital feedthrough clk vdd = 5v v w f i g u re 31. cl ock f e edt h roug h and m i ds c a l e t r ans i t i on g lit ch 03823-0-032 vwb1 (0x3f stored in eemem) vwb3 (0x3f stored in eemem) vdd = va1 = va3 = 3.3v gnd = vb1 = vb3 midscale preset restore rdac1 setting to 0x3f restore rdac3 setting to 0x3f vdd (no de- coupling caps) midscale preset f i g u re 32 .t eemem_ r es t o r e
ad5251/ad5252 rev. 0 | page 19 of 28 code (decimal) 03823-0-033 0 3 2 1 4 5 6 0 8 16 24 32 40 48 56 64 the o re tical i wb _ m a x (ma) r ab = 1k ? v a = v b = open t a =2 5 c r ab = 10k ? r ab = 50k ? r ab = 100k ? f i gur e 3 3 . ad52 51 i wb ma x vs . c o de code (decimal) 03823-0-034 0 3 2 1 4 5 6 0 3 2 6 4 9 6 128 160 192 224 256 the o re tical i wb _ m a x (ma) r ab = 1k ? v a = v b = open t a =2 5 c r ab = 10k ? r ab = 50k ? r ab = 100k ? f i gur e 3 4 . ad52 52 i wb ma x vs . c o de
ad5251/ad5252 rev. 0 | page 20 of 28 operational overview the ad5251/ad5252 are dual-channel digital potentiometers in 1 k?, 10 k?, 50 k?, or 100 k? that allow 64 and 256 linear resistance step adjustments. the ad5251/ad5252 employ double-gate cmos eeprom technology that allows resistance settings and user-defined data to be stored in the eemem registers. the eemem is nonvolatile, such that settings remain when power is removed. the rdac wiper settings are restored from the non-volatile memory settings during device power-up and can also be restored at any time during operation. the ad5251/ad5252 resistor wiper positions are determined by the rdac register contents. the rdac register acts like a scratch-pad register, allowing unlimited changes of resistance settings. rdac register contents can be changed using the devices serial i 2 c interface. the format of the data-words and the commands to program the rdac registers are discussed in the i2c interface detail description section. the four rdac registers have corresponding eemem memory locations that provide nonvolatile storage of resistor wiper position settings. the ad5251/ad5252 provide commands to store the rdac register contents to their respective eemem memory locations. during subsequent power-on sequences, the rdac registers are automatically loaded with the stored value. whenever the eemem write operation is enabled, the device activates the internal charge pump and raises the eemem cell gate bias voltage to a high level, essentially erasing the current content in the eemem register and allowing subsequent stor- age of the new content. saving data to an eemem register con- sumes about 35 ma of current and lasts about 26 ms. because of charge pump operation, all rdac channels may experience noise coupling during the eemem writing operation. the eemem restore time in power-up or during operation is about 300 s. note that the power up eemem refresh time depends on how fast v dd reaches its final value. as a result, any supply voltage decoupling capacitors limit the eemem restore time during power-up. figure 32 shows the power up profile where v dd , without any decoupling capacitors connected to it, is applied with a digital signal. the device initially resets the measured rdacs to midscale before reaching their final values during eemem restoration. in addition, users should issue a nop command 0 immediately after using command 1 to restore the eemem setting to rdac, to minimize supply current dissipation. directly reading user data from eemem does not require similar nop command execution. in addition to the movement of data between rdac registers and eemem memory, the ad5251/ad5252 provide other shortcut commands that facilitate the users programming needs, as shown in table 11. table 11. ad5251/ad5252 quick commands commmand description 0 nop 1 restore eemem content to rdac. user should issue nop immediately after this command to conserve power. 2 store rdac register setting to eemem. 3 decrement rdac 6 db (shift data bits right). 4 decrement all rdacs 6 db (shift all data bits right). 5 decrement rdac one step. 6 decrement all rdacs one step. 7 reset eemem contents to all rdacs. 8 increment rdac 6 db (shift data bits left). 9 increment all rdacs 6 db (shift all data bits left). 10 increment rdac one step. 11 increment all rdacs one step. 12C15 reserved. linear increment and decrement commands the increment and decrement commands (10, 11, 5, and 6) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the ad5251/ad5252. the adjustments can be directed to an individual rdac or to all four rdacs. 6 db adjustments (doubling/halving wiper setting) the ad5251/ad5252 accommodates 6 db adjustments of the rdac wiper positions by shifting the register contents to left/right for increment/decrement operations, respectively. commands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 db steps synchronously or asynchronously. incrementing the wiper position by +6 db is essentially doubling the rdac register value, while decrementing by C6 db is halving the register content. internally, the ad5251/ad5252 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. the maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. these functions are useful for various audio/video level adjustments, especially for white led brightness settings where human visual responses are more sensitive to large than small adjustments.
ad5251/ad5252 rev. 0 | page 21 of 28 digit a l input/output c o nfigur a t ion s d a is a d i g i t a l in p u t/o u t p ut wi t h a n op en -drai n mos f et t h a t r e q u ir es a p u l l - u p r e sis t o r fo r p r o p er co mm uni c a t ion. on t h e o t h e r hand , sc l a nd wp are d i g i t a l i n pu t s f o r w h i c h pu l l - u p r e sis t o r s a r e r e co mm e nde d t o minimize the mos f et s cr os s co nd uc t i o n c u r r en t w h e n t h e dr i v i n g sig n als a r e lo w e r t h a n v dd . scl an d wp h a ve e s d prote c t i on d i o d e s , a s s h ow n i n f i gur e 35 an d f i gur e 36. wp ca n be p e rm a n e n tl y ti e d t o v dd w i t h out a pu l l - up re s i stor i f th e w r i t e- p r o t ec t f e a t ur e i s n o t used . i f wp is lef t f l o a tin g , a n i n t e rnal cu rr e n t so u r c e p u ll s i t lo w t o e n a b le w r i t e- p r o t ect . i n a p plic a t io n s w h er e t h e de vi ce is n o t b e in g p r og ra mm e d o n a f r eq uen t basis, t h is al lo ws t h e p a r t t o defa u l t t o wr i t e-p r o t ec t af te r an y on e - t i me f a c t or y pro g r a m m i ng or f i el d c a l i br a t i o n w i t h out t h e u s e of an on b o ard pu l l - d ow n re s i stor . b e c a u s e t h er e a r e p r o t e c t i o n dio d es on a l l t h es e i n p u ts, t h eir sig n al le ve ls mu s t n o t b e g r e a t e r t h a n v dd t o p r e v en t fo r w a r d b i asi n g o f t h e dio d e s . 03823-0-035 gnd s cl v dd f i g u re 35. scl d i g i t a l i n put 03823-0-036 gnd inputs wp v dd f i g u re 36. equiv a le nt wp di gi ta l i n p u t mul t iple de vices on one bus the ad5251 /ad5252 a r e eq ui p p ed wi th tw o addr es sin g p i ns, ad1 an d ad0, tha t al lo w u p t o f o ur ad5251/ad5252s t o b e op e r a t e d on o n e i 2 c b u s. t o achie v e t h is r e s u l t , t h e s t a t es o f ad1 an d ad0 o n e a ch de vic e m u st f i rst b e de f i n e d . an ex am ple is s h o w n in t a b l e 12 a nd f i gur e 37. i n i 2 c p r o g ra mmi n g , e a ch de vice is is s u e d a dif f er en t s l a v e addr es s0101 1(ad1)(ad0) to c o m p l e te t h e a ddre s s i ng . tab l e 12. multip le dev i ces a d d r essin g a d 1 a d 0 de vic e a d dress e d 0 0 u 1 0 1 u 2 1 0 u 3 1 1 u 4 03823-0-016 v dd r p r p +5v v dd v dd u1 ad0 ad1 sda scl master u2 ad0 ad1 sda scl u3 ad0 ad1 sda scl u4 ad0 ad1 sda sda scl scl f i g u re 37. m u lt ip le a d 52 51 /a d5 2 52s on a s i ng l e bus terminal vol t a g e o p e r a t ion r a nge the ad5251 /ad5252 a r e desig n e d wi t h in t e r n al es d dio d es fo r p r o t e c t i o n ; t h es e di o d es als o s e t t h e b o u ndar y o f t h e t e r m inal op era t in g v o l t a g es. p o si ti v e sig n als p r es en t on t e r m inal a, b , o r w tha t excee d v dd are cl am p e d b y t h e f o r w a r d b i as e d dio d e . s i mil a rl y , n e g a ti v e s i g n als o n t e r m inal a, b , o r w tha t a r e m o r e n e ga t i v e t h a n v ss are a l s o cl am p e d ( s e e f i gur e 38). i n prac t i ce , us ers sho u ld n o t o p era t e v ab , v wa , a nd v wb t o be hig h er tha n t h e v o l t ag e acr o s s v dd to v ss , b u t v ab , v wa , a nd v wb h a ve no p o l a r i t y c o nst r ai n t . v ss v dd a w b 03823-0-018 f i g u re 38. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and v ss po wer-up and po wer-do wn sequences b e ca us e t h e esd p r o t e c t i o n dio d es limi t t h e vol t a g e co m p l i ance a t t e r m inals a, b , a nd w (s ee f i gur e 38), i t is im p o r t a n t t o po w e r - o n v dd /v ss bef o r e a p p l y i n g an y v o l t a g e t o t e r m inals a, b , a nd w . o t h e r w is e, t h e dio d e s a r e fo r w a r d-b i a s e d such t h a t v dd /v ss a r e p o w e r e d uni n te n t i o na l l y a n d m a y a f fe c t t h e r e st o f t h e us er s cir c ui t. simi la rl y , v dd /v ss sh o u ld b e p o w e r e d do w n las t . th e ide a l p o w e r - u p s e q u e n ce is in the f o l l o w in g o r der : gnd , v dd , v ss , dig i t a l i n p u ts, and v a /v b /v w . t h e ord e r of po w e ri n g v a , v b , v w , a nd t h e d i g i t a l in p u ts is no t im p o r t a n t, as l o ng a s t h e y are p o we re d af t e r v dd /v ss .
ad5251/ad5252 rev. 0 | page 22 of 28 l a y o ut an d power s u ppl y biasi n g i t is al wa ys a g o o d p r ac tic e t o em p l o y a co m p ac t, minim u m le ad-le n gth la you t desig n . th e l e ads t o t h e in p u t sh o u ld be as d i re c t a s p o ss ibl e , w i t h a m i n i m u m c o nd u c tor l e ng t h . grou nd p a th s sh o u l d ha v e lo w r e sis t an c e a nd lo w in d u c t a n c e . s i mi la rl y , i t is al s o g o o d p r ac tic e t o b y p a s s t h e p o w e r s u p p lies wi th q u al i t y ca p a ci t o rs. l o w eq ui valen t s e r i es resis t a n c e (es r ) 1 f t o 10 f ta n t al u m o r e l ec trol ytic ca p a ci t o rs s h o u l d b e a p plie d a t t h e su p p lies to mi ni mi ze an y t r a n si en t dist ur b a n c e a nd f i l t er lo w f r eq uen c y r i p p le . f i gur e 39 il l u s t ra t e s t h e bas i c s u p p l y b y p a s s ing co nf igura t io n f o r th e ad5251 /ad5252. v dd v dd v ss v ss gnd c3 ad5251/ad5252 c4 c1 + + c2 10 f 10 f 0.1 f 0.1 f 03823-0-039 f i g u r e 3 9 . p o w e r su pp l y by pa s s i n g the g r o u nd p i n o f th e ad5251/ad5252 is us ed p r ima r il y as a d i gi tal gr o u n d r e f e r e n c e . t o min i m i ze th e d i gi tal gr o u n d bo u n ce , t h e ad5251/ad5252 g r o u n d t e r m inal s h o u l d be jo in e d r e m o te l y t o t h e co mm on g r o u nd (s ee f i gur e 39 ). digit a l po tent iome t e r oper a t i o n the s t r u c t ur e o f t h e rd a c is de sig n e d t o em u l a t e t h e p e r f o r ma n c e o f a me cha n i c a l p o ten t iometer . t h e r d a c c o n t ai ns a s t r i n g of re s i stor s e g m e n t s , w i t h a n ar r a y of an a l o g swi t ch es ac t i n g as t h e w i p e r conn e c t i o n t o t h e r e sis t o r a r ra y . the n u m b er o f p o in ts is t h e r e s o l u t i o n o f t h e de v i ce . f o r exa m p l e , t h e ad5251/ad5252 em u l a t es 64 o r 256 co nn ec t i o n p o in ts wi t h 64 or 256 eq ual r e sista n c e , r s , al lo win g i t t o p r o v ide b e tt e r t h a n 1 . 5 % / 0 . 4 % s e tt a b i l i t y re s o lut i on . fi g u r e 4 0 pr ov i d e s a n e q u i v a l e n t d i a g r a m o f t h e c o n n e c t i o n s b e t w e e n th e th r e e t e rm i n a l s t h a t m a k e u p o n e c h a n n e l o f th e rd a c . s w i t ch es sw a a nd sw b a r e al wa ys o n , w h i l e on e o f swi t ch es sw(0) t o sw(2 nC 1 ) is on o n e a t a t i me , dep e n d in g o n t h e s e t t i n g de co de d f r o m t h e da t a b i t. b e c a us e t h e s w i t ch es a r e n o nideal, t h er e is a 75 ? wi p e r r e sis t a n ce, r w . w i p e r r e sis t a n c e is a f u nc t i on of su p p ly vol t age and te m p e r a t u r e ; l o we r su p p ly v o l t a g es an d hig h er t e m p er a t ur e s r e s u l t in hig h e r wi p e r r e sist a n ces. c o nsider a t ion o f w i p e r r e sist a n c e dy na mics is im p o r t an t i n a pplica t ion s w h ere acc u ra te p r e d i c t i o n o f o u t p u t re s i st anc e i s re q u i r e d . sw b sw(1) sw(0) b x r s r s sw a sw(2 n ?1) a x w x sw(2 n ?2) rdac wiper register and decoder r s = r ab /2 n r s digital c ircuitr y o mitted for c larit y 03823-0-040 f i gure 40. equiv a le nt r d a c struc t ure progr a mm able rheost a t oper a t ion i f ei t h er t h e w - to-b o r w - t o - a ter m inal is us e d as a va r i a b le re s i stor , t h e u n u s e d te r m i n a l c a n b e op e n e d or shor te d w i t h w ; s u c h o p era t io n is cal l ed rh eos t a t m o de (s ee f i gu r e 41). th e r e sis t a n ce t o lera n c e ca n ran g e 20%. a w b 03823-0-041 a w b a w b f i g u re 41. r h e o s t at m o de conf ig ur at i o n the n o minal r e sis t a n c e o f the ad5251/ad52 52 has 64 o r 256 co n t ac t p o i n ts a c cess e d b y t h e wi p e r t e r m ina l , pl us t h e b t e r m inal co n t ac t. th e 6 - o r 8-b i t da t a -w o r d in th e rd a c r e g i s t er is deco ded t o s e lec t one o f th e 64 o r 25 6 s e t t in gs. th e wi p e r s f i rs t conn ec tion s t a r ts a t th e b t e r m inal f o r da ta 0x00. this b- t e r m in a l co nn e c t i o n has a w i p e r con t ac t r e sist a n ce , r w , o f 75 ?, r e ga r d l e s s o f th e n o minal r e sis t a n ce . th e s e con d co nn ec t i o n (t h e ad5251 10 k? p a r t ) is th e f i rs t ta p p o in t w h er e r wb = 231 ? (r wb = r ab /64 + r w = 156 ? + 75 ?) f o r da ta 0x01, a n d s o o n . e a c h ls b da ta val u e in cr eas e m o v e s the wi p e r u p th e r e si s t o r la d d e r un til t h e la s t ta p po i n t i s r e a c h e d a t r wb = 9893 ?. s e e f i gur e 40 f o r a sim p l i f i ed diag ra m o f th e eq ui valen t rd a c cir c ui t. the g e n e ral e q u a t i o n t h a t det e r m i n es t h e dig i t a l l y p r ogra mm e d o u t p ut r e sist a n c e b e tw e e n w and b , is ad5251: r wb ( d ) = ( d /64) r ab + 75 ? (1) ad5252: r wb ( d ) = ( d /256) r ab + 75 ? (2) w h er e d is t h e de cima l e q ui v a l e n t d a t a con t aine d i n t h e r d a c la tch and r ab is t h e n o mina l end-to - e n d r e sist an ce.
ad5251/ad5252 rev. 0 | page 23 of 28 (%) d (code in decimal) 03823-0-042 0 25 50 75 100 0 16 32 48 63 r wa r wb f i gur e 4 2 . ad52 51 r wa (d) and r wb (d) vs . d ecimal c o d e table 13. r wb vs. cod e s; r ab = 10 k?, a ter m inal = o p e n d (de c ) r wb (?) o u tput s t a t e 6 3 9 9 1 8 f u l l s c a l e 3 2 5 0 7 5 m i d s c a l e 1 2 3 1 1 l s b 0 75 z e r o scale (wi p e r r e sistanc e ) n o t e th a t i n th e z e r o - s ca l e c o n d i t i o n , a 7 5 ? fi n i t e w i pe r r e sis t a n ce is p r es en t. c a r e sh o u ld b e tak e n t o limi t t h e c u r r en t co nd uc t i o n b e t w e e n w an d b i n t h is st a t e to no m o r e t h a n 5 ma co n t in u o us f o r a t o tal r e sis t a n c e o f 1 k?, o r a 20 ma p u ls e, to a v o i d deg r a d a t io n o r p o ssi b le dest r u c t io n o f t h e in t e r n al swi t ch co n t ac t. simi la r to t h e me cha n ic a l p o te n t io meter , t h e r e s i st an ce o f t h e rd a c bet w een w i per w a n d t e rm i n al a also p r od uces a d i gi tall y c o n t r o ll ed c o m p l e m e n t a r y r e s i s t a n c e , r wa . w h e n t h es e t e r m inals a r e us e d , t h e b t e r m inal ca n b e op e n e d . s e t t i n g t h e r e sis t a n ce val u e fo r r wa st ar ts a t a max i m u m v a lu e of re s i st anc e a nd de cr e a s e s a s t h e d a t a lo ade d i n t h e l a tch i n cr e a s e s in va l u e (s e e f i gur e 40). the ge n e ra l e q u a t i o n fo r t h is o p era t io n is ad5251: r wa ( d ) = [(64 C d )/64 ] r ab + 75 ? (3) ad5252: r wa ( d ) = [(256 C d )/2 56] r ab + 75 ? (4) table 14. r wa vs. codes; a d 52 51, r ab =10 k?, b termi n al ope n d (de c ) r wa (?) o u tput s t a t e 6 3 2 3 1 f u l l s c a l e 3 2 5 0 7 5 m i d s c a l e 1 9 9 1 8 1 l s b 0 1 0 0 7 5 z e r o s c a l e t h e t y pi c a l d i st r i but i on of r ab fr o m c h a n n e l - t o - c h a n n e l ma t c h e s abo u t 0.15% w i t h in a g i v e n de vice . on t h e o t h e r ha nd , d e vice -to - de vi ce ma tchi ng is p r o c ess-lo t dep e nden t wi t h 20% t o lera n c e . progr a mm able po ten t iome ter o p er a t ion i f al l t h r e e t e r m inals a r e us e d , t h e op era t ion is cal l e d p o t e n t i- o m e t er mo de and t h e m o st comm on co nf igur a t io n is t h e v o l t a g e divider o p era t ion (s e e f i gur e 43). 03823-0-043 a b w v i v c f i gure 43. p o tentiometer m o de c o nf ig ur ation i f the wi p e r r e sis t an ce is ig n o r e d , t h e tra n sf er f u n c tion is sim p ly ad5251: b ab w v v d v + = 64 (5) ad5252: b ab w v v d v + = 256 (6) a m o r e ac c u ra te ca lc u l a t ion, w h ich i n cl udes t h e w i p e r re s i st anc e e f f e c t , y i el d s a w ab w ab n w v r r r r d d v 2 2 ) ( + + = ( 7 ) w h er e 2 n is the n u m b er o f s t eps . u n li k e in rh eos t a t m o de o p era t ion w h ere t h e t o lera nce i s hig h , p o t e n t iom e t e r mo de op e r a t i o n y i el d s an a l mo st r a t i o m e t r i c f u nc t i on of d /2 n wi t h a rel a t i vely s m a l l e r ror c o n t r i bute d b y t h e r w t e r m s. th er efo r e , t h e t o lera n c e ef fe c t is al m o s t can c e l le d . simi la rly , t h e ra t i o m et r i c ad j u s t men t als o r e d u ces t h e t e m p er a t ur e co ef f i cien t ef fe c t t o 50 p p m / c, excep t a t lo w val u e co des w h er e r w do min a tes. p o t e n t iomet e r m o de o p er a t io ns in cl ude o t h e r a p plic a t io n s such a s op am p i n put , f e e d b a c k re s i st or ne t w or k s , a n d ot he r vo lt age s c al in g a p p l ic a t io n s . th e a, w , a nd b t e r m inals ca n in fac t be i n put or output te r m i n a l s , prov i d e d | v a |, |v w |, a n d |v b | d o n o t e x ceed v dd to v ss .
ad5251/ad5252 rev. 0 | page 24 of 28 u1 v 1 r sense 0.1k ? rdac1 10k ? rdac3 10k ? b b ad5252 ad8628 u2 v o vref +5v v+ v? 03823-0-045 v 2 appli c a t ions lc d p a n e l v co m ad j u st ment l a rg e l c d p a ne ls us ual l y r e q u ir e a n ad j u s t a b le v co m volt age cen t er e d a r o u nd 6 v t o 8 v wi t h 1 v sw in g and smal l s teps ad j u s t m e n t . thi s exa m ple r e p r es en ts co mm o n d a c a p pli- ca t i o n s w h er e t h e wi ndo w o f ad j u s t m e n t s is smal l a nd ce n t ere d a t an y leve l . h i g h v o l t a g e and hig h r e s o l u tio n d a cs ca n b e us ed b u t i t is fa r m o r e cos t -ef f e c t i v e to us e lo w v o l t a g e dig i t a l p o t e n t iom e t e rs wi th l e v e l s h if t i n g, s u ch as t h e ad5251 o r ad5252, t o ac hiev e t h e ob j e c t i v e . as s u m e a v co m v o l t a g e r e q u i r em en t o f 6 v 1 v wi th a 20 mv s t ep ad j u s t m e n t , as s h o w n in f i gur e 44. the ad5252 ca n be co nf igur e d in vol t a g e d i v i der m o de wi t h an op a m p ga in . w i t h 20% t o lera n c e acco un ted f o r b y th e ad5252, t h is cir c ui t ca n s t il l b e ad j u st ed f r o m 5 v t o 7 v wi th an 8 mv/st e p in t h e worst c a s e . f i gure 4 5 . c u rr ent- s e nsing a m p l i f ier . adjust able high po wer led driver f i g u re 4 6 s h o w s a c i rc u i t t h a t c a n d r ive t h re e to f o u r h i g h p o we r led s . th e ad p 1610 is a n ad j u sta b le bo os t r e gu la t o r tha t p r o v ide s ade q u a t e h e adr o o m and c u r r en t fo r t h e le d s . b e ca u s e i t s fb p i n v o l t a g e is 1.2 v , t h e dig i tal p o t e n t iomet e r ad5252 a nd t h e o p am p fo r m a n a v era g e ga in o f 12 fe e d b a ck n e tw o r ks th a t s e r v o th e s e n s i n g a n d f eed ba c k v o l t a g e s . a s a r e s u l t , t h e volt age a c ro ss r set i s re g u l a te d a rou nd 0 . 1 v , d e p e n d i n g on t h e ad5252 s s e t t ing. an ad j u s t ab le led c u r r en t is v dd u1 u2 v com +5v r2 10k r4 6k r3 18.5k r5 1k r1 350k c1 2.2p b ad5252 +14.4v +14.4v 20% 1% 6v 1v v+ v? 03823-0-044 set r led r v i set = ( 9 ) r set s h o u l d b e smal l t o co n s er ve p o w e r b u t l a rg e en o u g h t o limi t t h e maxim u m led c u r r en t. r3 sh o u ld als o b e us e d in p a ral l e l wi th t h e ad5252 t o limi t t h e led c u r r en t wi thin an achie v a b le ra n g e. f i g u re 44. a p ply 5 v d i g i t a l p o te nt i o met e r a d 5 2 5 1 in a 6 v 1 v a p p l i c at io n. /sd sw fb comp ss rt gnd in pwm c c 390pf c ss 10nf r o 100k ? r set 0.25k ? 10k ? w ba c8 0.1 f ad5252 adp1610 v out ad8591 u3 u1 u2 u1 +5v +5v v+ v? 03823-0-046 r3 200 ? r2 1.1k ? r1 100 ? r4 13.5k ? c3 10 f c2 10 f d1 d1 d2 d3 l1 10 f current -sensing amplifier the d u a l chan nel, sy n c hr on o u s u p da te, an d channel- to -cha n n el r e sis t a n ce ma t c hin g c h a r ac t e r i stics mak e t h e ad5251/ad5252 sui t ab le fo r c u r r en t s e n s in g a p pl ica t io n s , such as led br i g h t ne ss c o n t ro l. i n t h e c i rc u i t s h ow n i n fi g u re 4 5 , w h e n rd a c 1 and rd a c 3 a r e p r og ra mm e d t o t h e s a m e s e t t in g s , i t ca n b e sh o w n t h a t () ref n o v v v d d v + ? ? = 1 2 2 (8) a s a re su lt , t h e c u r r e n t t h rou g h a s e n s e re s i stor c o n n e c te d bet w een v 1 and v 2 ca n b e k n o w n. t h e p r o g r a m m a b i l i t y o f t h is cir c ui t ma k e s i t ada p t a b l e t o syst em s t h a t r e q u ir e dif f er en t s e n- si t i vi t i es . i f t h e o p a m p has v e r y lo w o f fs et a n d lo w b i as c u r r en t, t h e m a j o r s o u r c e of e r ror c o me s f rom t h e d i g i t a l p o te n t i o me te r cha nnel- to -channel r e sist an ce misma t ch, w h ich is ty p i ca l l y 0.15%. the cir c ui t acc u rac y is ab o u t 9 b i ts, w h i c h is ade q u a t e f o r led co n t r o l a n d o t h e r g e n e ral p u r p ose a p plica t io n s . f i gure 4 6 . hi gh p o w e r a d justa b l e led dri v er
ad5251/ad5252 rev.0 | page 25 of 2 8 outline dimensions 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153ab-1 f i gure 47. 1 4 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 14) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l s t e p r ab (k?) t e mper a t ur e ra n g e ( c) p a ck age descri ption p a ck age op t i o n f u ll c o ntainer qu a n t i ty br and i ng 1 ad5251bru1 64 1 ?40 to +85 tssop ru-14 96 b1 ad5251bru1-rl7 64 1 ?40 to +85 tssop ru-14 1,000 b1 ad5251bru10 64 10 ?40 to +85 tssop ru-14 96 b10 ad5251bru10- r l 7 6 4 1 0 ?40 t o + 8 5 t s s o p r u - 1 4 1 , 0 0 0 b 1 0 ad5251bru50 64 50 ?40 to +85 tssop ru-14 96 b50 ad5251bru50- r l 7 6 4 5 0 ?40 t o + 8 5 t s s o p r u - 1 4 1 , 0 0 0 b 5 0 ad5251bru100 64 100 ?40 to +85 tssop ru-14 96 b100 ad5251bru100 -rl7 64 100 ?40 to +85 tssop ru-14 1,000 b100 ad5251e v a l 6 4 1 0 e v alua t i o n boar d 1 ad5252bru1 256 1 ?40 to +85 tssop ru-14 96 b1 ad5252bru1-rl7 256 1 ?40 to +85 tssop ru-14 1,000 b1 ad5252bru10 256 10 ?40 to +85 tssop ru-14 96 b10 ad5252bru10- rl7 256 10 ?40 to +85 tssop ru-14 1,000 b10 ad5252bru50 256 50 ?40 to +85 tssop ru-14 96 b50 ad5252bru50- rl7 256 50 ?40 to +85 tssop ru-14 1,000 b50 ad5252bru100 256 100 ?40 to +85 tssop ru-14 96 b100 ad5252bru100 - r l 7 2 5 6 1 0 0 ?40 to + 8 5 t s s o p r u - 1 4 1 , 0 0 0 b 1 0 0 ad5252e v a l 2 5 6 1 0 e v alua t i o n boar d 1 1 in the pack age mark i ng, line 1 s h o w s the part numbe r; li ne 2 s h o w s the brand i ng inf o rmatio n, s u ch that b1 = 1 k ?, b10 = 10 k ?, b50 = 50 k ?, and b100 = 100 k ? ; li n e 3 sh ow s t h e da t e cod e i n yyww .
ad5251/ad5252 rev. 0 | page 26 of 28 notes
ad5251/ad5252 rev. 0 | page 27 of 28 notes
ad5251/ad5252 rev. 0 | page 28 of 28 notes p u r c h a se o f li c e n s e d i 2 c c o m p on en t s o f an a l og devi c e s or on e of i t s subli c en s e d a s s oci a t e d c o m p a n i e s c o n v ey s a li c e n s e f o r t h e pur c h a ser un der t h e p h i li p s i 2 c p a te nt r i ghts t o us e the s e co mpo n e n ts in an i 2 c sy st em , pr o v i d e d t h a t t h e sy st em c o n f orm s t o t h e i 2 c stand a rd sp ecif ica t ion as d e f i ned b y p h il ips. ? 2 004 ana l og de v i ce s, i n c . al l rig h t s r e s e r v e d . t r ad em a r k s and re gis t e r e d t r a d e m a r ks a r e the p r o p e r ty o f the i r r e sp ec t i v e ow ne rs. d03823-0 - 6/04 (0)

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